View BD9536FV_4083859.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

technical note high-performance regulator ic series for pcs 2ch switching regulators for desktop pc BD9536FV ? description BD9536FV is a 2ch switching regulator c ontroller that can generate low output voltages (0.7v to 5.5v) from a wide input voltage range (7.5v to 15v). high efficiency for the switching regulator can be achieved due to its internal n-mosfet power transistor. the ic also incorporates a new technology called h 3 reg tm , a rohm proprietary control method which facilitates ultra-high transient response against changes in load. for prot ection and ease of use, the ic also incorporates soft start, variable frequency, and short circuit protecti on with timer latch functions. this switching regulator is specially designed for dram and power supplies for graphics chips. ? features 1) 2ch h 3 reg tm dc/dc converter controller 2) thermal shut down (tsd), under-voltage lock-out (uvlo), adjustable over current protection (ocp) : det ected fet ron, over voltage protection (ovp), short circuit protection (scp) built-in 3) soft start function to minimize rush current during startup 4) adjustable switching frequency ( f = 200 khz ? 600 khz) 5) ssop-b28 package 6) built-in 5v power supply for fet driver 7) integrated bootstrap diode ? applications lcd, game consoles, desktop pcs sep. 2008
2/17 maximum absolute ratings (ta=25 ) parameter symbol limit unit input voltage vin 16 * 1 v boot voltage boot1/2 23 *1 v boot-sw voltage boot 1-sw1, boot2-sw2 7 *1 v hg-sw voltage hg1-sw1, hg2-sw2 7 * 1 v lg voltage lg1/2 5vreg v output voltage v out 1/2 7 *1 v output feedback voltage fb1/2 5vreg v fs voltage fs1/2 5vreg v 5vreg voltage 5vreg 7 *1 v current limit setting voltage ilim1/2 5vreg v logic input voltage en1/2, ctl1/2 7 * 1 v power dissipation 1 pd1 0.8 *2 w power dissipation 2 pd2 1.06 *3 w operating temperature range topr -20 +100 storage temperature range tstg -55 +150 junction temperature tjmax +150 *1 not to exceed pd. *2 reduced by 6.4mw for each increase in ta of 1 over 25 (when not mounted on a heat radiation board ) *3 reduced by 8.5mw for increase in ta of 1 over 25 . (when mounted on a board 70.0mm 70mm 1.6mm glass-epoxy pcb.) operating conditions (ta=25 ) parameter symbol min. max. unit input voltage vin 7.5 15 v boot voltage boot1/2 4.5 20 v sw voltage sw1/2 -0.7 15 v boot-sw voltage boot1-sw 1, boot2-sw2 4.5 5.5 v logic input voltage en 1/2, ctl1/2 0 5.5 v output voltage v out 1/2 0.7 5.5 v min on time tonmin - 100 ns this product should not be used in a radioactive environment.
3/17 electrical characteristics (unless otherwise noted, ta=25 , v cc =5v, v in =12v, v en1 =v en2 =3v, v out1 =v out2 =1.8v, r fs =75k ) parameter symbol limit unit condition min. typ. max. [general] vin bias current i in - 1.6 2.5 ma vin standby current i in_ stb - 0 10 a v en1 =v en2 =0v en low voltage 1,2 v en _low 1,2 gnd - 0.3 v en high voltage 1,2 v en _high 1,2 2.2 - 5.5 v en bias current 1,2 i en1,2 - 14 20 a [5v linear regulator] 5vreg standby voltage 5vreg_stb - - 0.1 v v en1 =v en2 =0v 5vreg output voltage 5vreg 4.8 5.0 5.2 v v in =7.5v to 15v ireg=0ma to 10ma maximum current ireg 50 - - ma [under-voltage lock-out] 5vreg threshold voltage 5vreg _uvlo 3.75 4.20 4.65 v 5vreg:sweep up 5vreg hysteresis voltage d5vreg _uvlo 100 160 220 mv 5vreg:sweep down [ovp block] fb threshold voltage 1,2 fb _ovp1,2 0.75 0.85 0.95 v [h 3 reg tm control block] on time1 ton 1 480 600 720 ns r fs1 =75k max on time 1 tonmax 1 3.0 4.0 5.0 s min off time 1 toffmin 1 600 900 - ns on time 2 ton 2 480 600 720 ns r fs2 =75k max on time 2 tonmax 2 3.0 4.0 5.0 s min off time 2 toffmin 2 600 900 - ns [fet block] hg high side on resistance 1,2 r hghon1,2 - 3.0 6.0 hg low side on resistance 1,2 r hglon1,2 - 2.0 4.0 lg high side on resistance 1,2 r lghon1,2 - 2.0 4.0 lg low side on resistance 1,2 r lglon1,2 - 0.5 1.0 [over current protection block] current limit threshold voltage1_1,2 v ilim 11,2 80 100 120 mv r ilim =100k reverse current limit threshold voltage 1_1,2 v r eilim 11,2 80 100 120 mv r ilim =100k [output voltage detection block] fb1 threshold voltage 1 fb1-1 0.615 0.625 0.635 v ctl1/2=0v or 3v fb1 threshold voltage 2 fb1-2 0.640 0.650 0.660 v ctl1=0v, ctl2=3v fb1 threshold voltage 3 fb1-3 0.590 0.600 0.610 v ctl1=3v, ctl2=0v fb2 threshold voltage fb2 0.640 0.650 0.660 v ctl low voltage 1,2 v ctl_l ow 1,2 gnd - 0.5 v ctl high voltage 1,2 v ctl_high1,2 vcc-0.5 - vcc v fb1/2 input current i fb -1 - 1 a vout discharge current i vout 5 10 - ma v out =1v, en=0v [scp block] threshold voltage 1,2 v thscp 1,2 ref1/2 0.70 ref1/2 0.80 ref1/2 0.90 v charge current (scp) i scp 1 2 3 a charge current (ovp) i ovp 4 8 12 a delay setting voltage v scp 1.05 1.2 1.35 v
4/17 block diagram pin configuration pin function pin no. pin name pin function 1 ctl1 1ch output voltage setting control pin 1 :see p13/17 2 vout1 output voltage sence pin 1 3 fb1 output voltage feedback pin 1 4 ref1 reference voltage pin 1/ soft start time setting pin 1 (0.625v 25mv select) :see p13/17 5 i lim 1 1ch ocp setting pin 6 fs1 switching frequency adjustable pin 1 7 gnd sense gnd 8 scp timer latch delay time setting pin for short circuit protection 9 fs2 switching frequency adjustable pin 2 10 i lim 2 2ch ocp setting pin 11 ref2 reference voltage pin 2/ soft start time setting pin 2 (0.65v) 12 fb2 output voltage feedback pin 2 13 vout2 output voltage sense pin 2 14 ctl2 1ch output voltage setting control pin 2 :see p13/17 15 en2 enable input pin 2 (0 0.3v:off, 2.2 5.5v:on) 16 boot2 hg driver power supply pin 2 17 hg2 high side fet gate driver pin 2 18 sw2 high side fet source pin 2 19 lg2 low side fet gate driver pin 2 20 5vreg reference voltage inside ic (5v voltage / always on) 21 vin battery voltage sense pin 22 vcc power supply input pin 23 pgnd power gnd 24 lg1 low side fet gate driver pin 1 25 sw1 high side fet source pin 1 26 hg1 high side fet gate driver pin 1 27 boot1 hg driver power supply pin 1 28 en1 enable input pin 1 (0 0.3v:off, 2.2 5.5v:on) BD9536FV ctl1 1 v out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 fb1 ref1 i lim 1 fs1 gnd scp fs2 i lim 2 ref2 fb2 v out 2 ctl2 en1 boot1 hg1 sw1 lg1 pgnd v cc v in 5v reg lg2 sw2 hg2 boot2 en2 thermal protection r s q tsd delay h 3 reg tm controlle r block 5vreg gnd boot1 hg1 sw1 lg1 pgnd 27 26 25 24 23 7 fs2 reference block uvlo en2 boot2 hg2 sw2 lg2 15 16 17 18 19 9 5vreg 20 21 ovp ovp driver circuit r s q h 3 reg tm controller block uvlo ilim2 scp tsd drive r circuit fb1 3 en1 28 fb2 12 ref2 0.85 fb1 ovp1 0.85 fb2 fs1 scp 8 5vreg 5vreg en2/uvlo v out 2 en1/uvlo v out 1 pgnd 2 v out 1 logic input v out 2 v in v out 1 v in v out 2 v in 13 v in v in en1 5vreg uvlo ilim1 scp tsd + - ref2 0.8 fb2 + - ref1 0.8 fb1 scp en2 5vreg 6 ctl1 1 ctl2 14 ref1 sw1 ocp sw2 ocp dac + - + - 5 i lim 1 i lim 2 10 ovp ovp2 22 5vreg vcc 11 4 ref1 bg bg bg + - v in + - bg
5/17 reference data fig.1 dac switch1 fig.3 dac switch 3 fig.4 dac switch 4 fig.5 en startup (ref1) fig.6 en startup (ref2) fig.2 dac switch 2 (100 s/div) (100 s/div) v out 1 (50mv/div) ref1 (50mv/div) ctl1 (5v/div) ctl2 (5v/div) v out 1 (50mv/div) ref1 (50mv/div) ctl1 (5v/div) ctl2 (5v/div) v out 1 (50mv/div) ref1 (50mv/div) ctl1 (5v/div) ctl2 (5v/div) (100 s/div) (100 s/div) v out 1 (50mv/div) ref1 (50mv/div) ctl1 (5v/div) ctl2 (5v/div) v out 1 (1v/div) ref1 (500mv/div) en1 (5v/div) v out 2 (1v/div) ref2 (500mv/div) en2 (5v/div) v out 2 (1v/div) v out 1 (1v/div) hg1 (10v/div) hg2 (10v/div) fig.7 v out 1 scp function fig.8 v out 2 scp function fig.9 v out 1 v out 2 scp function v out 2 (1v/div) v out 1 (1v/div) hg1 (10v/div) hg2 (10v/div) v out 2 (1v/div) v out 1 (1v/div) en2 (5v/div) en1 (5v/div) fig.10 v out 1transient responce fig.11 v out 1 transient responce fig.12 v out 2 transient responce v out 1 (200mv/div) hg1/lg1 (10v/div) i out 1 (5a/div) v out 1 (200mv/div) hg1/lg1 (10v/div) i out 1 (5a/div) v out 2 (50mv/div) hg2/lg2 (10v/div) i out 2 (5a/div) (200 s / div) (200 s/div) (20ms/div) (20ms/div) (500ms/div) (20 s/div) (20 s/div) (10 s/div)
6/17 reference data 0.0 0.5 1.0 1.5 2.0 -101030507090 ta [ ] iin [ma] fig.13 v out 2 transient responce v out 2 (50mv/div) hg2/lg2 (10v/div) i out 2 (5a/div) fig.15 ta vs iin (active) (10 s/div) 0 1 2 3 4 5 6 7 8 9 10 -101030507090 ta [ ] iin [ a] fig.14 ta vs iin (standby) 100 100 4.0 4.5 5.0 5.5 6.0 -101030507090 ta [ ] vreg5v [v] 100 0.80 0.82 0.84 0.86 0.88 0.90 -101030507090 ta [ ] fb [v] 100 -120 -110 -100 -90 -80 -101030507090 ta [ ] sw[mv] 100 fig.19 ta vs scp threshold (2ch) fig.20 ta vs delay setting voltage fig.21 ta vs ocp threshold 100 1.0 1.1 1.2 1.3 1.4 1.5 -101030507090 ta [ ] scp [v] 100 0.40 0.44 0.48 0.52 0.56 0.60 -101030507090 ta [ ] fb1 [v] 100 fig.16 ta vs vreg5v fig.17 ta vs ovp threshold fig.18 ta vs scp threshold (1ch) fig.22 efficiency (1ch) 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 iout [a] efficiency [%] 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 iout [a] efficiency [%] 0.40 0.44 0.48 0.52 0.56 0.60 -101030507090 ta [ ] fb2 [v] 100 fig.23 efficiency (2ch) 0.50 0.54 0.58 0.62 0.66 0.70 -101030507090 ta [ ] ref[v] 100 fig.24 ta vs ref ref1 ref2
7/17 evaluation board circuit evaluation board parts list designation value part no. company designation value part no. company r1 0 mcr03 series rohm c10 0.1uf kyocera r2 10 mcr03 series rohm c11 0.1uf kyocera r3 1k mcr03 series rohm c12 10uf kyocera r4 100k mcr03 series rohm c13 330pf kyocera r5 1k mcr03 series rohm c14 100pf kyocera r6 100k mcr03 series rohm c15 330uf os-con sanyo r7 0 mcr03 series rohm c16 0.1uf kyocera r8 68k mcr03 series rohm c17 - kyocera r9 0 mcr03 series rohm c18 10uf kyocera r10 58k mcr03 series rohm c19 10uf kyocera r11 - mcr03 series rohm c20 330pf kyocera r12 11.5k mcr03 series rohm c21 100pf kyocera r13 6.5k mcr03 series rohm c22 330uf spcap panasonic r14 - mcr03 series rohm c23 0.1uf kyocera r15 6.5k mcr03 series rohm c24 - kyocera r16 6.5k mcr03 series rohm d1 rb083l-20 rohm c1 1uf kyocera d2 rb083l-20 rohm c2 10uf kyocera l1 3.9uh b966as toko c3 0.1uf kyocera l2 1.6uh 962bs toko c4 33pf kyocera m1 sp8k4 (q1) rohm c5 0.01uf kyocera m2 sp8k4 (q2) rohm c6 33pf kyocera m3 rss100n03 rohm c7 0.01uf kyocera m4 rss100n03 rohm c8 0.1uf kyocera u1 - BD9536FV rohm c9 0.01uf kyocera u1 BD9536FV vin 5vreg en1 i lim 1 ref1 en2 i lim 2 ref2 gnd fs2 fb2 v out 2 lg2 sw2 hg2 boot2 pgnd lg1 sw1 hg1 boot1 r7 c11 c12 1.8v gnd pgnd1 pgnd2 pgnd gnd lg1 sw1 hg1 r10 c7 r6 r5 en2 c5 c6 r3 en1 c4 sw2 5vreg 5vreg r1 vin 12v c1 c2 vin r8 c18 c19 1.2v lg2 sw2 hg2 vin c10 c8 m4 m1 sw1 ssop-b28 ctl1 ctl2 logic input logic input v out 1 fb1 fs1 scp vcc r2 c3 r4 r9 c9 m3 l1 c13 c16 c17 m2 d1 c15 r12 r13 r11 c14 l2 c20 c23 c24 d2 c22 r15 r16 r14 c21 21 20 22 28 5 4 15 10 1 14 11 7 9 12 13 19 18 17 16 8 6 3 2 23 24 25 26 27
8/17 pin descriptions ? en1 (28 pin) / en2 (15 pin) when the input voltage on the en pin reaches at least 2.2 v, the switching regulator becomes active. at voltages less than 0.3 v, the switching regulator becomes inactive, and the input cu rrent drops to 10 ua or less. thus the ic can be controlled from 2.5 v, 3.3 v or 5 v power supplies. ? 5vreg (20 pin) 5.0 v reference voltage output pin. if at least 2.2 v is supplied to either the en1 or en2 pin, the reference output is switche d on. this pin supplies 5.0 v at up to 50 ma. inserting a 10 uf capacitor (with a x5r or x7r rating) between the 5vreg and gnd pins is recommended. ? i lim 1 (5 pin) / i lim 2 (10 pin) the ic monitors the voltage between the sw pin and pgnd pi n as a control for the output current protection (ocp) mechanism. the voltage at which ocp engages is determined by the resistance value connected to the ilim pin. this also allows for compatibility with fets of various r on values. ? v in (21 pin) the ic determines the duty cycles internally based upon the input voltage on this pin. therefor e, variations in voltage on this pin can lead to highly unstable operation. this pin also acts as the voltage input to t he internal switching regulator block, and is sensitive to t he impedance of the power supply. attaching a bypass capacitor or rc filter on this pin as appropriate for the application is recommended. ? fs1 (6 pin) / fs2 (9 pin) this pin is used to adjust the switching frequency via an extern al resistor. the frequency range is from 200 khz to 600 khz. ? boot1 (27 pin) / boot2 (16 pin) this pin supplies voltage used for driving the high-side fe t. maximum absolute ratings are 23v from gnd and 5.5v from sw. boot voltage swings between vin + 5vreg and 5vreg during active operation. ? hg1 (26 pin) / hg2 (17 pin) this pin supplies voltage used for driv ing the gate of the high-side fet. th is voltage swings between boot and sw. high-speed gate driving for the high side fet can be achieved due to its low on-resistance (3 ? when hg = high, 2 ? when hg = low) of the driver. ? sw1 (25 pin) / sw2 (18 pin) this pin acts as the source connection to the high-side fe t. maximum absolute rating is 16v from gnd. sw voltage swings between vin and gnd. ? lg1 (24 pin) / lg2 (19 pin) this pin supplies voltage used for driv ing the gate of the low-side fet. th is voltage swings between vdd and pgnd. high-speed gate driving for the low-side fet can be achieved due to its low on-resistance (2 ? when lg = high, 0.5 ? when lg = low) of the driver. ? pgnd (23 pin) this pin acts as the ground connection to the source of the low-side fet. ? gnd (7 pin) this is the ground pin for all internal analog and digital power supplies. ? scp (8 pin) this pin allows for adjustment of the latch timer used for shor t circuit protection. when voltage on this pin drops lower than 80% of ref, the output will switch off and remain latched after the specified time interval. when the uvlo circuit becomes active, or when en is pulled low, the timer-latching function is disabled. ? v out 1 (2 pin) / v out 2 (13 pin) this is the output voltage sense pin; this pin features an integrated discharge fet used to discharge the output capacitor when status is set to off. ? fb1 (3 pin) / fb2 (12 pin) this is the output feedback pin. while channel 2 internal refe rence voltage is fixed at 0.650v, channel 1 internal reference voltage is adjustable depending on the input conditions of the ctl1 and ctl2 pins. ? ref1 (4 pin) / ref2 (11 pin) this is the reference/adjustment pin for soft start time. output rise time is determined by t he rc time constant of the ic?s internal resistance (50k ? typ.) and an external capacitor. ? vcc (22 pin) this is the power supply pin for all internal circuitry. this pin can be supplied directly by a 5v source, or via an rc filter (10 ? , 0.01 uf) from the 5vreg pin. ? ctl1 (1 pin) / ctl2 (14 pin) these pins allow for the adjustment of the internal voltage re ference (ref1) for channel 1. the pins recognize a logic hi at vcc-0.5 v or above, and a logic lo at 0.5 v or below. refer to the voltage adjustment table for ref1 on page 13.
9/17 explanation of operation the BD9536FV is a 2ch switching regulator cont roller incorporating rohm?s proprietary h 3 reg controlla control system. when vout drops due to a rapid load change, the system qui ckly restores vout by extending the ton time interval. h 3 reg tm control (normal operation) (vout drops due to a rapid load change) timing chart ? soft start function ts s (on )= 50k ? css [sec] rush current: iin = co vout ts s [a] t on = ref vin 1 f [sec] ??? (1) ??? (2) ??? (3) when fb falls below the threshold voltage (ref), a drop is detected, activating the h 3 reg controlla system. hg output is determined by the formula above. when fb (v out) drops due to a rapid load change, and the voltage remains below ref after the programmed t on time interval has elapsed, the system quickly restores v out by extending the t on time, improving transient response. soft start is utilized when the en pin is set high. current control takes effect at startup, enabling a moderate ?ramping start? on the ouput voltage. soft start timing and input current are determined via formula (2) and (3) below. soft start time: (css: soft start capacitor; co: output capacitor) fb ref hg lg en ref iin t ss(on) v out fb ref hg io lg t on +
10/17 timing chart ? over current protection circuit ? timer latch type short circuit protection ? output over voltage protection when output voltage rises to or above ref x 1.2, output over-voltage protection engages after the set time t scp / 8 has elapsed. during this protection period, the low-side fet opens completely for maximum reduction of output voltage (lg = high, hg = low). output voltage can be restored either by reconnecting the en pin or disabling uvlo. hg lg ref 1.2 switching v out delay setting voltage 1.2v during normal operation, when vout falls below ref, hg switches high during fo r the period of time t on (p8). however, if the current through the inductor exceeds the i limit threshold, hg will switch off. a fter the max on time period elapses, hg switches high again if the output voltage is lower than the specified voltage level, and if i l is lower than the i limit level. t on t on hg lg i l t on short protection time setting tscp= 1.2(v) c scp 2 a(typ) [sec] ??? (4) t on short protection engages when output falls to or belo w ref x 0.8. when the programmed time period elapses, output is latched off to prev ent damage to the ic. output voltage can be restored either by reconnecting the en pin or disabling uvlo. short circuit protection time is determined via formula (4) below. scp fb scp en/uvlo t scp ref 0.8 delay setting voltage 1.2v
11/17 external component selection 1. inductor (l) selection passing a current larger than the inductor?s rated current wi ll cause magnetic saturation in the inductor and decrease system efficiency. when selecting an inductor, be sure to allow enough margin to assure that peak current does not exceed the inductor?s rated current value. to minimize possible inductor damage and maximize efficiency, choose a inductor with a low (dcr, acr) resistance. 2. output capacitor (c o ) selection also, give due consideration to the conditions in formula (9) below for output capacitance, bearing in mind that output rise ti me must be established within the soft start time frame: note: an improper output capacitor may cause startup malfunctions. 3. input capacitor (cin) selection a low-esr capacitor is recommended to re duce esr loss and maximize efficiency. i l = (v in -v out ) v out l v in f [ a ] ??? ( 5 ) i l =0.3 i out max. [a] ??? (6) l= (vin-vout) vout i l vin f [ h ] ??? ( 7 ) v out = i l esr+esl i l /t on ??? (8) co Q tss (limit-i out ) v out ??? ( 9 ) input capacitor i rms =i out v out ( v in -v out ) v in [ a ] ??? ( 10 ) where v in =2 v out , i rms = i out 2 il vin il l co vout output ripple current vin l co vout esr output capacitor vin l co vout cin esl the inductance value has a major influence on output ripple current. a s formula (5) below indicates, the greater the inductance o r switching frequency, the lower the ripple current. the proper output ripple current setting is about 30% of maximum out p ut current. ( i l : output ripple current; f: switch frequency) when determining a proper output capacitor, be sure to factor in the equivalent series resistance and equivalent series in ductance required to set the output ripple voltage to 20mv or more. also, make su re the capacitor?s voltage rating is high enough for the set output voltage (including ripple). output ripple voltage is determined as in formula (8) below. ( i l : output ripple current; esr: c o equivalent series resistance, esl: equivalent series inductance) tss: soft start time limit: over current detection i out : output current in order to prevent transient spikes in voltage, the input capacitor selected must have a low enough esr resistance to fully support a large ripple current on the output. the formula for ripple current irms is given in equation (10) below: lg sw hg lg sw hg lg sw hg
12/17 4. mosfet selection 5. determining detection resistance pmain = p ron + p gate + p tran psyn = p ron + p gate v in -v out v in r on i out 2 +5vreg f v dd v in l co v out synchronous switch main switch main mosfet power dissipation is computed as follows: (ron: on-resistance of fet; qg: fet gate capacitance; f: switching frequency; crss: fet inverse transfer function; i drive : gate peak current) synchronous mosfet power dissipation is computed as follows: = ??? (12) v out v in r on i out 2 +qg(hi) f 5vreg+ v in 2 crss i out f i drive = ??? (11) qg loss is also incurred as internal power dissipation in the ic: for example: if qg(hi) = 20nq, qg(low) = 50nq, f = 300khz, p ic(drive) = qg(hi) f + qg(low) f (vin-5vreg) ??? (13) = p ic(drive) = 20n 300k +50n 300k (12-5) = 0.147w the over-current protection function is controlled via the voltage detected between the sw and pgnd pins ? i.e., the on-resistance of the synchronous fet. the current limit value is determined by formula (14) below: 10k r ilim r on i lim = (r ilim : resistance for setting over-current protection limit, r on : low side fet on-resistance ) v in l co v out [a] ??? (14) pgnd sw r ilim
13/17 0 500 1000 1500 2000 2500 0 50 100 150 200 250 rfs [k ] ton[ns] 6. setting frequency 7. output voltage setting the ic will try to maintain output voltage such that v ref P v fb . however, the actual output voltage will also reflect the average ripple voltage value. the output voltage is set via a resistive voltage divider betw een the output and the fb pin. the formula for output voltage is given in (16) below: output voltage= it is recommended that r1 and c1 be connected in parallel to the fb pin. in low output ripple applications ( v < 20 mv), add r add and c add as shown in the above application circuit. for value settings, refer to the tool provided separately. ref2 voltage is fixed at 0.65 v; however, ref1 voltage can be adjusted via the ctl1 and ctl2 pins. ref1 voltage setting table ctl1 ctl2 ref1 l l 0.625 v h l 0.600 v l h 0.650 v h h 0.625 v freq = v out v in t on 1,2ch r1+r2 r2 h 3 reg tm controlla s rq driver circuit output voltage fb r1 r2 1 2 ref + i l esr ??? (16) esr ref v in c1 c add * r add * the on-time (t on ) at steady state is determined by the resistance value connected to the fs pin. however, the actual sw rise/fall time is influenced b y the gate capacitance and switching speed of the external mosfet, thereby increasing t on . the frequency is determined by the following formula afte r t on , input current and the ref voltage are fixed. ??? (15) consequently, the actual overall frequency becomes lower than the value obtained by the formula above. t on is also influenced by ?dead time,? which occurs when the output current approaches the 0a range in continuous mode; frequency in this output range will also be lower than the set oscillation frequency. it is recommended to check the steady-state frequenc y while pulling a large current (but without saturating the output inductor). from top vin=7.5v 12v 15v
14/17 i/o equivalent circuits 16pin, 27pin (boot1/2) 15pin, 28pin (en1/2) 6pin, 9pin (fs1/2) 4pin, 11pin (ref1/2) 20pin (5vreg) 1pin, 14pin (ctl1/2) 26pin, 17pin (hg1/2) 25pin, 18pin (sw1/2) 24pin, 19pin (lg1/2) boot boot sw vdd hg sw 5vreg boot 1/2 boot hg
15/17 operation notes (1) absolute ma ximum ratings use of the ic in excess of absolute maximum ratings (such as the input voltage or operating temperature range) may result in damage to the ic. assumptions should not be made regarding the state of the ic (e.g., short mode or open mode) when such damage is suffered. if operational values are expected to exceed the maximum ratings for the device, consider adding protective circuitry (such as fuses) to eliminate the risk of damaging the ic. (2) power supply polarity connecting the power supply in reverse polarity can cause damage to the ic. take precautions when connecting the power supply lines. an external power diode can be added. (3) power supply lines in order to minimize noise, pcb layout should be designed such that separate, low-impedance power lines are routed to the digital and analog blocks. additionally, a coupling capacitor should be inserted bet ween all power input pins and the ground terminal. if electrolytic capacitors are used, keep in mind that their capacitance characteristics are reduced at low temperatures. (4) gnd voltage the potential of the gnd pin must be the minimum potential in the system in all operating conditions. (5) thermal design use a thermal design that allows for a sufficient margin for power dissipation (pd) under actual operating conditions. (6) inter-pin shorts and mounting errors use caution when orienting and positioning the ic for mounting on printed circuit boards. improper mounting may result in damage to the ic. shorts between output pins or between out put pins and the power supply and gnd pins caused by poor soldering or foreign objects may result in damage to the ic. (7) operation in strong electromagnetic fields using this product in strong electromagnetic fields may cause ic malfunction. caution should be exercised in applications where strong electromagnetic fields may be present. (8) aso - area of safe operation when using the ic, ensure that operating conditions do not exceed absolute maximum ratings or aso of the output transistors. (9) thermal shutdown (tsd) circuit the ic incorporates a built-in thermal shutdown circuit, which is designed to turn the ic off completely in the event of thermal overload. it is not designed to protect the ic from damage or guarantee its operation. ics should not be used after this function has activated, or in applications where the operation of this circuit is assumed. (10) testing on application boards when testing the ic on an application board, connecting a capacitor directly to a low-impedance pin may subject the ic to stress. always discharge capacitors completely after each process or step. the ic?s power supply should always be turned off completely before connecting or removing it from a jig or fi xture during the evaluation process. to prevent damage from static discharge, ground the ic during assembly and use similar precautions during transport and storage. tsd on temp. [c] (typ.) hysteresis temp. [c] (typ.) BD9536FV 175 15
16/17 (11) regarding input pins of the ic this monolithic ic contains p+ isolation and p substrate laye rs between adjacent elements in order to keep them isolated. pn junctions are formed at the intersection of these p layers with the n layers of other elements, creating parasitic diodes and/or transistors. for example (refer to the figure below): ? when gnd > pin a and gnd > pin b, the pn junction operates as a parasitic diode ? when gnd > pin b, the pn junction operates as a parasitic transistor parasitic diodes occur inevitably in the structure of the ic, and the operation of these parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. accordingly, conditions that cause these diodes to operate, such as applying a voltage lower than the gnd voltage to an input pin (and thus to the p substrate) should be avoided. (11) ground wiring pattern when using both small-signal and large-current gnd traces , the two ground traces should be routed separately but connected to a single ground potential within the application in order to avoid variations in the small-signal ground caused by large currents. also ensure that the gnd traces of external components do not cause variations on gnd voltage. power dissipation resistor transistor (npn) n n n p + p + p p substrate gnd parasitic element pin a n n p + p + p p substrate gnd parasitic element pin b c b e n gnd pin a p aras iti c element pin b other adjacent elements e b c gnd p aras iti c element example of ic structure ambient temperature (ta) mounted on board 70mm 70mm 1.6mm glass-epoxy pcb j-a=117.6 /w 0 25 75 100 125 150 50 0.4 0.2 0 [ ] 0.8 1.0 0.6 [w] 100 1.06w power dissipation (pd) 0.8w only ic j-a=156.3 /w 1.2
17/17 type designations (selections) for ordering b d 9 5 3 6 f D e 2 product name package type taping type name e2= embossed carrier tape ? bd9536 ? fv : ssop-b28 v unit:mm) ssop-b28 0.15 0.1 0.1 1.15 0.1 1 0.65 7.6 0.3 5.6 0.2 28 10.0 0.2 0.3min. 14 15 0.22 0.1 0.1 ta p e q uantit y direction of feed embossed carrier tape 2000pcs e2 (holding the reel with the left hand and pulling out the tape with the right, pin 1 will be on the upper left-hand side.) reel direction of feed 1pin 1234 1234 1234 1234 1234 1234 1234 1234 orders should be placed in multiples of package quantity. catalog no.08t451a '08.9 rohm ?
appendix1-rev3.0 thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact your nearest sales office. rohm customer support system the americas / europe / asia / japan contact us : webmaster@ rohm.co. jp www.rohm.com copyright ? 2008 rohm co.,ltd. 21 saiin mizosaki- cho, ukyo-ku, kyoto 615-8585, japan tel : +81-75-311-2121 fax : +81-75-315-0172 appendix notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of rohm co.,ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing rohm's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from rohm upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, rohm shall bear no respon- sibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. rohm does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by rohm and other parties. rohm shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products are not designed to be radiation tolerant. while rohm always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possi bility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. rohm shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which re quires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). rohm shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the f oreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law.

▲Up To Search▲

Price & Availability of BD9536FV

	To Download BD9536FV Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .